The semiconductor industry has been advanced to the field of Nanometer Scale technologies. The fabrication of the nonvolatile memories also follows the trend of the size reduction. The nonvolatile memory includes various types of devices which have been developed for specific applications. One of the applications of flash memory is BIOS for computers. The high-density nonvolatile memories can be applied as the mass storage of portable handy terminals, solid-state camera and PC cards. It is because that the nonvolatile memories exhibit many advantages, such as memory retention without power, fast access time, low power dissipation in operation, and robustness.
The formation of nonvolatile memories toward the trends of low supply power and fast access, because these requirements are necessary for the application of the mobile computing system. Nonvolatile memory devices include a floating gate to store charges and an element for electrically placing charge in and removing the charges from the floating gate. At present, the low voltage nonvolatile memory is applied with a voltage of about 3V to 5V during charging or discharging the floating gate. In order to attain high tunneling efficiency, the thickness of the dielectric between the floating gate and substrate has to be scaled down due to the supply voltage is reduced. The data program method of a non-volatile memory device includes a method using Fowler-Nordheim (FN) tunneling. In FN tunneling, a high voltage is applied to a control gate to induce a high electric field in a tunnel oxide layer, and electrons of a semiconductor substrate pass the tunnel oxide layer and are injected into a floating gate. During the mode of erasing, the bias may apply on the source to discharge the electron from the floating gate to the source of a memory device.
Currently, the SOC (system on chip) desires memory with high operation speed and integrated in one single chip. For example, the single polysilicon processing may integrate with other devices such as transistors. The typical non-volatile memory employs stack gate memories by double polysilicon processing. One type of the memories uses trapping layer instead of floating gate (FG) to hold the carrier. The memory cells are constructed with a trapping ONO or ON layer. The memory cell generally includes a P-type silicon substrate and two PN junctions between N+ source (or drain regions) and P type substrate, a nitride layer sandwiched between two oxide layers and a polycrystalline layer. To program or write the cell, voltages are applied to the drain and the gate and the source is grounded. These voltages generate an electric field along the length of the channel from the source to the drain. This electric field causes electrons to be drawn off the source and begin accelerating towards the drain. The hot electrons are generated at the boundary between drain and channel during the acceleration.
In the prior art, please refer to U.S. Pat. Nos. 4,881,108; 5,768,192 to Eitan B. entitled “Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping”, filed on 16 Jun. 1998. The charge trapping memory may also be referred to U.S. Pat. No. 6,335,554 to Yoshikawau and Kuniyoshi, entitled “Semiconductor Memory”. The patent disclosed a memory with ONO structure. Further article teaches the memory with ONO stacked layer could also be found. Please refer to the article, Chan, T. Y. et al, “A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device,” IEEE Electron Device Letters, vol. EDL-8. No. 3, March 1987.
Furthermore, another type structure called FinFET is developed recently. The channel region of the device is similar to a Fin structure that is why it was named as FinFET device. The source/drain and the channel are formed in a single crystallographic orientation silicon layer. Gate oxide is subsequently formed over the silicon layer, followed by forming a gate wrapping the channel region, thereby creating the creating the dual gate structure. Thus, the channel width of the FinFET device is wider than the prior structure. It allows generating higher driving current than that of the conventional FET device. In the prior art, please refer to U.S. Pat. Nos. 4,881,108; 6,800,910 to Lin; Ming-Ren, and assigned to Advanced Micro Devices, Inc., entitled “FinFET device incorporating strained silicon in the channel region”. The filing date is Dec. 31, 2002. Other reference could refer to U.S. Pat. No. 6,770,516, assigned to Taiwan Semiconductor Manufacturing Company, entitled “Method of forming an N channel and P channel FINFET device on the same semiconductor substrate”. The filing date is Sep. 5, 2002.